RELEASED
PM7350 S/UNI-DUPLEX
DATA SHEET
PMC-1980581
ISSUE 5
DUAL SERIAL LINK PHY MULTIPLEXER
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
PM7350
S/UNI
-
DUPLEX
TM
S/UNI-DUPLEX
DUAL SERIAL LINK, PHY MULTIPLEXER
DATA SHEET
RELEASED
ISSUE 5: APRIL 2000
RELEASED
PM7350 S/UNI-DUPLEX
DATA SHEET
PMC-1980581
ISSUE 5
DUAL SERIAL LINK PHY MULTIPLEXER
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
REVISION HISTORY
Issue No.
Issue Date
Originator
Details of Change
Issue 5
April 2000
Phil Walston
Updated analog parameters,
I
DDOP
, thermal info and corrected
register description typos.
Release to production.
Issue 4
February
2000
Phil Walston
Updated to incorporate Revision
B changes outinled in previous
Errata. Change bars highlight
specific changes.
Issue 3
June 1999
James
Lamothe
Changed confidentiality notices
for document's public release.
Issue 2
May, 1999
Jeff Brown
Extensive updates throughout
Issue 1
May, 1998
Jeff Brown
First release
RELEASED
PM7350 S/UNI-DUPLEX
DATA SHEET
PMC-1980581
ISSUE 5
DUAL SERIAL LINK PHY MULTIPLEXER
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
i
CONTENTS
1
FEATURES .............................................................................................. 1
2
APPLICATIONS ....................................................................................... 3
3
REFERENCES......................................................................................... 4
4
APPLICATION EXAMPLES ..................................................................... 5
5
BLOCK DIAGRAM ..................................................................................11
6
DESCRIPTION ...................................................................................... 12
7
PIN DIAGRAM ....................................................................................... 14
8
PIN DESCRIPTION................................................................................ 15
9
FUNCTIONAL DESCRIPTION............................................................... 45
9.1
PARALLEL BUS INTERFACE ..................................................... 45
9.2
CLOCKED SERIAL DATA INTERFACE ...................................... 57
9.3
HIGH-SPEED SERIAL INTERFACE ........................................... 61
9.4
CELL BUFFERING AND FLOW CONTROL ............................... 71
9.5
TIMING REFERENCE INSERTION AND RECOVERY ............... 75
9.6
JTAG TEST ACCESS PORT....................................................... 76
9.7
MICROPROCESSOR INTERFACE ............................................ 76
9.8
INTERNAL REGISTERS ............................................................. 80
9.9
REGISTER MEMORY MAP ........................................................ 80
10
NORMAL MODE REGISTER DESCRIPTION ....................................... 84
11
TEST FEATURES DESCRIPTION ...................................................... 170
11.1 RAM BUILT-IN-SELF-TEST ...................................................... 173
11.2 JTAG TEST PORT .................................................................... 177
RELEASED
PM7350 S/UNI-DUPLEX
DATA SHEET
PMC-1980581
ISSUE 5
DUAL SERIAL LINK PHY MULTIPLEXER
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
ii
12
OPERATION ........................................................................................ 182
12.1 MICROPROCESSOR INBAND COMMUNICATION ................. 182
12.2 INTERACTION BETWEEN BUS AND LVDS CONFIGURATIONS
.................................................................................................. 184
12.3 MAXIMUM CELL BIT RATE ...................................................... 193
12.4 MINIMUM PROGRAMMING ..................................................... 194
12.5 JTAG SUPPORT ....................................................................... 196
13
FUNCTIONAL TIMING......................................................................... 203
13.1 SCI-PHY/ANY-PHY INTERFACE .............................................. 203
13.2 CLOCKED SERIAL DATA INTERFACE .................................... 208
14
ABSOLUTE MAXIMUM RATINGS ....................................................... 210
15
D.C. CHARACTERISTICS ....................................................................211
16
MICROPROCESSOR INTERFACE TIMING CHARACTERISTICS..... 215
17
A.C. TIMING CHARACTERISTICS...................................................... 219
18
ORDERING AND THERMAL INFORMATION...................................... 226
19
MECHANICAL INFORMATION............................................................ 227
RELEASED
PM7350 S/UNI-DUPLEX
DATA SHEET
PMC-1980581
ISSUE 5
DUAL SERIAL LINK PHY MULTIPLEXER
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
iii
LIST OF REGISTERS
REGISTER 0X00: MASTER RESET AND IDENTITY / LOAD PERFORMANCE
METERS ................................................................................................ 85
REGISTER 0X01: MASTER CONFIGURATION .............................................. 86
REGISTER 0X02: MASTER INTERRUPT STATUS ......................................... 88
REGISTER 0X03: MISCELLANEOUS INTERRUPT STATUS ......................... 90
REGISTER 0X04: CLOCK MONITOR.............................................................. 92
REGISTER 0X05: SERIAL LINKS MAINTENANCE ......................................... 94
REGISTER 0X06: EXTENDED ADDRESS MATCH (LSB)............................... 96
REGISTER 0X07: EXTENDED ADDRESS MATCH (MSB).............................. 97
REGISTER 0X08: EXTENDED ADDRESS MASK (LSB) ................................. 98
REGISTER 0X09: EXTENDED ADDRESS MASK (MSB) ................................ 99
REGISTER 0X0A: OUTPUT ADDRESS MATCH ........................................... 100
REGISTER 0X0B: CONFIGURATION PINS STATUS.................................... 101
REGISTER 0X0C: SCI-PHY/ANY-PHY INPUT CONFIGURATION 1 ............. 103
REGISTER 0X0D: SCI-PHY/ANY-PHY INPUT CONFIGURATION 2 ............. 105
REGISTER 0X0E: SCI-PHY/ANY-PHY INPUT INTERRUPT ENABLES ........ 107
REGISTER 0X0F: SCI-PHY/ANY-PHY INPUT INTERRUPT STATUS ........... 108
REGISTER 0X10: INPUT CELL AVAILABLE ENABLE (LSB)......................... 109
REGISTER 0X11: INPUT CELL AVAILABLE ENABLE (2ND) ........................ 109
REGISTER 0X12: INPUT CELL AVAILABLE ENABLE (3RD) .........................110
REGISTER 0X13: INPUT CELL AVAILABLE ENABLE (MSB).........................110
REGISTER 0X14: SCI-PHY/ANY-PHY OUTPUT CONFIGURATION..............112
REGISTER 0X15: SCI-PHY/ANY-PHY OUTPUT POLLING RANGE ..............115
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